Conventional DRAMs use sensing schemes that require amplifiers capable of sensing small sense signals. One way to amplify small sense signals has been shown to be a cross-couple sense amplifier, as is well known in the art. These cross-couple sense amplifiers require balanced true and complement bitlines to perform and operate reliably.
In conventional DRAMs, the sense signal from a memory cell is generated by charge sharing the charge stored in the memory cell with a precharged bitline, and then comparing the developed sense signal on the precharged bitline to a reference bitline.
To achieve maximum density, a large number of memory cells are typically connected to a single bitline to reduce the area overhead of the local amplifier. However, adding cells to a bitline also increases the bitline capacitance, and consequently reduces the transfer ratio (Ccell/(Cb1+Ccell)), which in turn reduces the developed sense signal. Typically the number of bits (memory cells) per bitline is chosen to minimize the number of sense amps (overhead) while maintaining enough sense signal to reliably detect the stored state of a memory cell.
The amplitude of the sense signal ΔVb1 from a memory cell is a function of the cell capacitance, the bitline capacitance and the voltage swing to the bitline high precharge, as set forth in the following formulas which includes the transfer ratio.ΔVb1=(Vcell−Vb1h)*(Ccell/(Cb1+Ccell)), and                where                    Vcell=voltage stored in the memory cell            Vb1h=bitline precharge level voltage (e.g., 1.2-1.8V)            Ccell=cell capacitance            Cb1=bitline capacitance                        
One attempt at increasing the transfer ratio is set forth in U.S. Pat. No. 6,738,300 in which a local sense amplifier having four transistors is utilized. However, this design does not readily allow an early masked write, where a subset of bits along a wordline may be written prior to wordline activation. Additionally, global bitline charging current must be distributed through a path shared with neighboring cells, which must also be decoded with row address. The charging current disadvantageously flows parallel to the wordline creating data pattern dependent voltage drops.
A smaller design local bitline sense amplifier is desired that requires less space and overcomes deficiencies of the prior art. Additionally, further decreases in bitline capacitance and increases in the transfer ratio are desired.